Static Random-Access Memory is a volatile semiconductor memory technology that stores each bit using a bistable circuit, commonly implemented as a flip-flop-like arrangement of multiple transistors. Unlike dynamic random-access memory, SRAM does not require periodic refresh to preserve its state while electrical power remains available. This makes SRAM particularly attractive for applications requiring very low access latency and rapid repeated access. Its principal disadvantage is lower density and higher cost per stored bit because an SRAM cell requires substantially more transistors than a typical DRAM cell. SRAM is therefore generally used for relatively small, high-performance memory structures rather than as the primary large-capacity memory in general-purpose computers.
A conventional SRAM cell is commonly based on a six-transistor structure, often called a 6T SRAM cell. Two cross-coupled inverters form a bistable storage element that maintains one of two stable states, while additional access transistors connect the cell to bitlines when it is selected. The cross-coupled configuration continuously reinforces the stored state while power is supplied. Reading and writing involve controlling wordlines and bitlines through peripheral circuitry. Other SRAM cell designs can use different transistor counts or specialised structures, particularly when optimising for density, leakage, performance or low-voltage operation.
SRAM's speed and predictable access characteristics make it particularly valuable inside processors. Modern CPUs commonly use SRAM-based cache memories at several levels, with very small L1 caches positioned extremely close to execution units and larger L2 or shared L3 caches providing greater capacity. Cache memory stores recently or frequently accessed instructions and data so that processors do not have to retrieve every value from slower main memory.
The exact cache hierarchy varies by processor architecture, but SRAM's low latency and random-access behaviour make it well suited to this role. The limited physical area available on a processor die makes the higher cost per bit acceptable because cache capacity is selected to provide a useful balance between hit rate and silicon cost.
SRAM is also used in applications beyond processor caches. Networking equipment, embedded systems, microcontrollers, high-performance communication hardware and specialised buffers can employ SRAM where rapid access and deterministic behaviour are valuable. Some processors use SRAM for register files, translation structures, queues and other internal storage. Embedded SRAM can be integrated directly into microcontrollers and systems-on-chip, reducing external memory requirements and communication overhead. In some specialised systems, larger SRAM arrays are used as scratchpad memory that software or hardware manages explicitly rather than relying entirely on automatic cache mechanisms.
SRAM's absence of refresh simplifies certain aspects of operation, but it does not mean SRAM consumes no power. While a cell is holding a state, leakage and other circuit currents can consume energy, and read or write operations activate peripheral circuitry. As semiconductor feature sizes shrink, leakage current becomes an important design consideration, especially in large SRAM arrays. Designers may employ techniques such as power gating, reduced-voltage operation, banking and specialised cell architectures to manage energy consumption. The trade-off between leakage, stability, density and speed becomes particularly significant in low-power systems.
SRAM cell stability is a major engineering concern. Because the stored state depends on a pair of mutually reinforcing inverters, variations in transistor characteristics, supply voltage and environmental conditions can affect the ability of the cell to retain and switch states reliably. Static noise margin is one measure used to characterise the robustness of an SRAM cell against disturbances. Manufacturing variability becomes increasingly important as transistor dimensions shrink, causing designers to balance read stability, write ability, retention and area. Advanced SRAM design therefore involves substantial circuit-level optimisation rather than merely connecting more generic transistors together.
SRAM and DRAM are often compared simply as "fast RAM" and "slow RAM", but their differences are more fundamental. SRAM uses bistable transistor circuits, avoids periodic refresh and generally provides lower latency, while DRAM uses capacitor-based cells requiring refresh and achieves much greater density. DRAM is therefore economically suitable for large main-memory capacities, whereas SRAM is economical only at relatively small capacities when its performance advantages justify its silicon cost. Both remain volatile and lose stored state when power is removed. Their complementary characteristics are a central reason modern computers use a memory hierarchy rather than a single universal memory technology.
SRAM has remained important despite decades of research into alternative memory technologies because processor architectures place exceptional value on very low latency and high bandwidth. Its integration directly onto processor dies allows cache structures to operate at speeds closely coupled to processor execution. However, SRAM occupies substantial silicon area, and increasing cache size can produce diminishing performance returns while raising manufacturing cost and leakage.
Emerging processor architectures therefore carefully divide limited SRAM capacity among instruction caches, data caches and shared caches according to workload and architectural objectives. SRAM should consequently be understood not simply as an older type of RAM but as a specialised high-performance memory technology whose density, speed, power and stability characteristics make it particularly valuable for small, latency-critical storage structures.
